DRV8305_15 Datasheet, PDF (36/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
7.6.7.4 IC Operation (address = 0x9)
Table 17. IC Operation Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Flip_OTS
0x0
Enable OTS
b'0 - Disable OTS
b'1 - Enable OTS
9
R/W
DIS_VPVDD_UVLO2 0x0
Disable PVDD_UVLO2 fault and reporting
b'0 - PVDD_UVLO2 enabled
b'1 - PVDD_UVLO2 disabled
8
R/W
DIS_GDRV_FAULT 0x0
Disable gate driver fault and reporting
b'0 - Gate driver fault enabled
b'1 - Gate driver fault disabled
7
R/W
EN_SNS_CLAMP
0x0
Enable sense amplifier clamp
b'0 - sense amplifier clamp is not enabled
b'1 - sense amplifier clamp is enabled limiting output to about
3.3 V
6:5
R/W
WD_DLY
0x1
Watch dog delay
b'00 - 10 ms
b'01 - 20 ms
b'10 - 50 ms
b'11 - 100 ms
4
R/W
DIS_SNS_OCP
0x0
Disable SNS overcurrent protection fault and reporting
b'0 - SNS OCP enabled
b'1 - SNS OCP disabled
3
R/W
WD_EN
0x0
Watch dog enable
b'0 - Watch dog disabled
b'1 - Watch dog enabled
2
R/W
SLEEP
0x0
Put device into sleep mode
b'0 - Device awake
b'1 - Device asleep
1
R/W
CLR_FLTS
0x0
Clear faults
b'0 - Normal operation
b'1 - Clear fault bits
0
R/W
SET_VCPH_UV
0x0
Set charge pump undervoltage threshold level
b'0 - 4.9 V
b'1 - 4.6 V
36
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