DRV8305_15 Datasheet, PDF (13/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, T_A = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
t_{VDS_PULSE}
nFAULT pin reporting pulse
stretch length for V_DS event
PHASE SHORT PROTECTION
V_{SNSOCP_TRIP} Phase short protection limit Fixed voltage
DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
MIN
TYP
MAX UNIT
56
µs
2
V
6.6 SPI Timing Requirements (Slave Mode Only)
t_{SPI_READY}
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
t_{HD_SDI}
t_{D_SDO}
t_{HD_SDO}
t_{SU_SCS}
t_{HD_SCS}
t_{HI_SCS}
tACC
t_DIS
SPI read after power on
Minimum SPI clock period
PVDD > V_{PVDD_UVLO1}
Clock high time
Clock low time
SDI input data setup time
SDI input data hold time
SDO output data delay time, CLK high to SDO valid C_L = 20 pF
SDO output hold time
SCS setup time
SCS hold time
SCS minimum high time before SCS active low
SCS access time, SCS low to SDO out of high impedance
SCS disable time, SCS high to SDO high impedance
MIN
NOM
MAX UNIT
5
10 ms
100
ns
40
ns
40
ns
20
ns
30
ns
20
ns
40
ns
50
ns
50
ns
400
ns
10
ns
10
ns
Figure 1. SPI Slave Mode Timing Definition
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