DRV8305_15 Datasheet, PDF (24/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
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7.3.10.4 Low-Side Source Monitoring (SNS_OCP)
The DRV8305 monitors the voltage on the SLX pins for high-current events like phase shorts that may cause the
voltage on those pins to exceed 2 V. The device will put the FETs into a high-impedance state to avoid damage.
7.3.11 Undervoltage Reporting and Undervoltage Lockout (UVLO) Protection
The DRV8305 implements appropriate undervoltage responses in order to protect the system. Fault / Warning
Classes and Recovery lists the details of the monitors and their response and recovery sequences.
Under-voltage is monitored on PVDD, AVDD, VCPH, and VCP_LSD.
The UVLO protection fault may be completely disabled for the PVDD undervoltage condition using a SPI register
command. In this case, the fault is still reported in the register.
The UVLO protection may never be completely disabled for the VCPH or VCP_LSD in OPERATING mode
because this may indicate a short condition that could damage the DRV8305.
7.3.11.1 Battery Overvoltage Protection (PVDD_OV)
The DRV8305 implements appropriate overvoltage responses in order to protect the system.
PVDD is monitored for overvoltage conditions. If the overvoltage threshold is tripped, a warning is issued and the
event is reported in the status registers. The device takes no action.
7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)
If VCPH or VCP_LSD exceed the overvoltage threshold due to potential issue related to the charge pumps (for
example, short of external charge pump capacitor or charge pump, an overvoltage fault is triggered).
7.3.11.3 Overtemperature (OT) Warning and Protection
A multi-level temperature detection circuit is implemented:
• Flag Level 1: Level 1 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 2: Level 2 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 3: Level 3 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 4: Level 4 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Warning Level: Overtemperature warning only. Warning is reported on nFAULT for 64 µs and can be read
through SPI.
• Fault Level: Overtemperature fault and latched shut down of gate driver and charge pump Fault will be
reported to nFAULT pin.
SPI operation is still available and register settings will be retained in the device during OTSD operation as long
as PVDD is still within defined operation range.
The details of the fault will be reported into a register that can be read back through SPI.
7.3.11.4 dV/dt Protection
The DRV8305 gate driver implements a strong pulldown scheme for preventing dV/dt turn on of external FETs.
After a FET has been turned off using the selected sink slew rate setting, the internal state machine will turn on a
stronger pulldown if it senses that the opposite FET on that phase has been commanded to turn on. This allows
the systems designer to decouple the optimum slew rate setting selection for EMI and power from the pull down
required to prevent dV/dt turn on.
7.3.11.5 VGS Protection
The DRV8305 gate driver uses a multilevel level protection scheme to protect the external FET from VGS
voltages that may damage the gate of the external FET.
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