DRV8305_15 Datasheet, PDF (17/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
7.3 Feature Description
7.3.1 Three-Phase Gate Driver
The DRV8305 provides three half-bridge drivers, each driver is capable of driving two N-type MOSFETs, one for
the high side and one for the low side.
Both the high side (GHX to SHX) and the low side (GLX to SLX) are implemented as floating gate drivers.
The gate driver uses a charge pump architecture which enables an extended voltage operating range to support
a variety of application requirements.
7.3.2 Operating Modes
The DRV8305 can be operated in three modes, to support various commutation schemes.
• Table 1 shows six independent PWM inputs with the truth table.
Table 1. 6-PWM Truth Table
INHX
INLX
GHX
GLX
1
1
L
L
1
0
H
L
0
1
L
H
0
0
L
L
• Three independent high-side PWM inputs (low-side complimentary PWMs generated internally).
In this mode all activity on INLA, INLB and INLC is ignored.
Table 2. 3-PWM Truth Table
INHX
INLX
GHX
GLX
1
X
H
L
0
X
L
H
• One single PWM that uses internally stored 6-step block commutation tables. In this mode of operation,
DRV8305 can be operated using a single PWM sourced from a low cost microcontroller. The PWM is applied
on pin PWM_IN (INHA) from the microcontroller along with three GPIO pins PHC_0 (INLA), PHC_1 (INHB),
PHC_2 (INLB) that serve to set the bits of a three bit register. The PWM may be operated from 0-100% duty
cycle. The three bit register is used to select the state of each of the phases for a total of eight states
including an align and stop state. The 1-PWM mode tables will use all the applicable settings from the control
registers as set up by the user.
An additional and optional GPIO (INHC) can be used to facilitate the insertion of dwell states or phase current
overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve
motion through the reduction of abrupt current direction changes when switching between states. INHC must
be high when the states are changed and the dwell state will exist until INHC is taken low. If the dwell states
are not being used, the INHC pin can be simply tied low.
In this mode all activity on INLC is always ignored.
The commutation tables ( Table 3 and Table 4) may be selected through the appropriate SPI register.
Copyright © 2015, Texas Instruments Incorporated
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