DRV8305_15 Datasheet, PDF (30/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 SPI
SPI is used to set device configuration, operating parameters, and read out diagnostic information. The
DRV8305 SPI operates in slave mode.
The SPI input data (SDI) word consists of a 16-bit word with 11-bit data and 5-bit (MSB) command. The SPI
output data (SDO) word consists of 11-bit register data. (The first 5 bits (MSB) are to be ignored.)
A valid frame must meet following conditions:
• Clock must be low when nSCS goes low.
• It should have 16 full clock cycles.
• Clock must be low when nSCS goes high.
Data is always shifted out on the rising edge of the clock in the same frame following the 5-bit MSB.
Data is always sampled on the falling edge of the clock in the same frame following the 5-bit MSB.
When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high-
impedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads
into the shift register based on 5-bit command.
The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the
response bit is serially shifted out on the SDO pin with MSB shifted out first.
While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI
command bits are decoded to determine the register address and access type (read or write). The MSB will be
shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error and
the data will not be written into the destination address. If it is a write command, the data will be ignored.
For a write command, the existing data in the register being written to is shifted out on SDO following the 5-bit
MSB.
SCS should be taken high for at least 500 ns between frames.
7.5.1.2 SPI Format
SPI input data control word is 16-bit long, consisting of:
• 1 read or write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]
SPI output data response word is 11-bit long (first 5 bits are ignored) and its content is the content of the register
being accessed
For a Write transaction: The response word is the data currently in the register being written to.
For a Read Command: The response word is the data currently in the register being read.
Table 7. SPI Input Data Control Word Format
R/W
ADDRESS
DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 8. SPI Output Data Response Word Format
DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command X
X
X
X
X D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30
Submit Documentation Feedback
Product Folder Links: DRV8305
Copyright © 2015, Texas Instruments Incorporated