DRV8305_15 Datasheet, PDF (37/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

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DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
7.6.7.5 Shunt Amplifier Control (address = 0xA)
Table 18. Shunt Amplifier Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
DC_CAL_CH3
0x0
DC Calibration of CS amplifier 3
b'0 - Normal operation
b'1 - DC calibration mode
9
R/W
DC_CAL_CH2
0x0
DC Calibration of CS amplifier 2
b'0 - Normal operation
b'1 - DC calibration mode
8
R/W
DC_CAL_CH1
0x0
DC Calibration of CS amplifier 1
b'0 - Normal operation
b'1 - DC calibration mode
7:6
R/W
CS_BLANK
0x0
Current shunt amplifier blanking time
b'00 - 0 ns
b'01 - 500 ns
b'10 - 2.5 µs
b'11 - 10 µs
5:4
R/W
GAIN_CS3
0x0
Gain of CS amplifier 3
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
3:2
R/W
GAIN_CS2
0x0
Gain of CS amplifier 2
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
1:0
R/W
GAIN_CS1
0x0
Gain of CS amplifier 1
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
7.6.7.6 Voltage Regulator Control (address = 0xB)
Table 19. Voltage Regulator Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Reserved
0x0
9:8
R/W
VREF_SCALING
0x1
VREF Scaling
b'00 - RSVD
b'01 - k = 2
b'10 - k = 4
b'11 - RSVD
7:5
R/W
Reserved
0x0
4:3
R/W
SLEEP_DLY
0x1
Delay to power down VREG after SLEEP
b'00 - 0 µs
b'01 - 10 µs
b'10 - 50 µs
b'11 - 1 ms
2
R/W
DIS_VREG_PWRGD 0x0
0:1
R/W
VREG_UV_LEVEL
0x2
VREG undervoltage set point
b'00 - VSET-10%
b'01 - VSET-20%
b'10 - VSET-30%
b'11 - VSET-30%
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