DRV8305_15 Datasheet, PDF (20/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
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Select a TDRIVE time that is longer than the time needed to charge or discharge the gate capacitances. IDRIVE
and TDRIVE are selected based on the size of external FETs used and the desired rise and fall times. These
registers must be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and
TDRIVE are too low for a given FET, then the FET may not turn on completely. TI suggests to adjust these
values in-system with the required external FETs to determine the best possible setting for any application.
Note that TDRIVE will not increase the PWM time and will simply terminate if a PWM command is received while
it is active. A good starting point is to select a TDRIVE that is about 2× longer than the external FET switching
rise (turn ON) and fall (turn OFF) times.
The IDRIVE/TDRIVE state machine protects against dV/dt turn on of a FET due to switching of the phase nodes.
A strong pulldown current source of value I_PULLDOWN is switched on between (GHX to SHX) or (GLX to SLX),
every time an opposing FET is commanded to turn on.
7.3.6 Slew Rate/Slope Control
Control of the FET VDS rise and fall times during the Miller region of the FET is one of the most important
parameters for optimizing emitted radiations and power. The rise and fall times also influence the energy and
duration of the diode recovery inductive spikes and also dV/dt turn on of the LS FET.
The ability of a driver to control the rise and fall times across the entire range of gate drive temperature, voltage,
and process variation is essential to design robust systems. The key control knob is the ability to turn on and turn
off the external FET with the least amount of variation.
The DRV8305 uses temperature compensated constant current sources up to 80-mA (sink) and 70-mA (source)
current. The current source architecture helps eliminate the temperature, process, and load-dependent variation
associated with internal and external series limiting resistors.
For higher currents, internal series resistors are used to minimize the power losses associated with mirroring
such large currents.
The 12 settings that are available on the DRV8305 allow the user to optimize the system using only SPI
commands. This flexibility allows the system designer to tune the performance of the driver for different operating
conditions through software alone.
The slew rate settings may be set separately for source and sink values and can also be set separately for the
high-side FETs (the high sides of all three phases share the same setting) and the low-side FETs (the low sides
of all three phases share the same settings)
7.3.7 Current Shunt Amplifiers
The DRV8305 includes three high performance low-side current shunt amplifiers for accurate current
measurement. The current amplifiers provide output bias up to 2.5 V to support bidirectional current sensing.
Current shunt amplifier has following features:
• Each of the three current sense amplifiers can be programmed and calibrated independently.
• The independent current shunt amplifiers may be used either for sensing current through individual phase
shunt resistors or the total current delivered to the motor through a single shunt resistor.
• Programmable gain: four gain settings through SPI command
• Internally or externally provided reference voltage to set output bias for amplifiers. Reference voltage is
internally sourced from DRV8305 voltage regulator VREG, if also used to power microcontroller. It can
alternatively be applied externally on the VREG pin.
• Programmable output bias scaling. The scaling factor k can be programmed through SPI to be equal to, half
or a fourth of the reference voltage.
• Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any
rising or falling edge (any of the outputs) of the internal gate driver gate signals. The blanking time is applied
to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked
when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge.
Note that the blanking time options do not include delay from internal amplifier loading or delays from the
trace or component loads on the amplifier output. The programmable blanking time may be overridden to
have no delay (default value).
• Minimize DC offset and drift through temperature with DC calibrating through SPI command. When DC
calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating
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