DRV8305_15 Datasheet, PDF (28/53 Pages) Texas Instruments – DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator

DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
7.3.13 Fault / Warning Classes and Recovery
7.3.13.1 Reg 09h CLR_FLTS
When CLR_FLTS bit is set to 1, all expired faults (latch/warn) will be cleared from the SPI status register. Also,
the nFAULT pin will be released on the event of an expired Latched fault. CLR_FLTS provides a software reset
option to DRV8305. The effect on nFAULT pin and SPI status registers is the same as pulling EN_GATE pin low
and taking it HIGH.
CLR_FLTS bit self clears to 0 after SPI status register is reset and nFAULT pin is released.
Table 6. Fault / Warning Reporting and Handling
CLASS
nFAULT
PWRGD
Latched
Low
No action
Warning
Toggles with 64-
µs period
No action
Report only (VDS Toggles with 64-
mode)
µs period
No action
Real time
Not reported
No action
No action
No action
No action
Latched +
PWRGD
Low
Low for minimum
of 64 µs
SPI REPORT
Yes
Yes
Yes
Yes
No
Yes
DEVICE RECOVERY SEQUENCE
Toggle EN_GATE (Faults clear on
rising edge of EN_GATE)
OR
Write Reg 09h CLR_FLTS bit set 1
Read SPI status register 0x01 to
acknowledge warning (otherwise
nFAULT will continue to toggle)
Read SPI status register 0x01 to
acknowledge warning (otherwise
nFAULT will continue to toggle)
Read SPI register to capture real
time status
None
Toggle EN_GATE (Faults clear on
rising edge of EN_GATE)
OR
Write Reg 09h CLR_FLTS bit set 1
SPI REPORT
RECOVERY
Bit clears only on
successful fault
recovery
Bit clears on register
read only if condition
has passed
Bit clears on register
read only if condition
has passed
Bit clears after
condition has passed
None
Bit clears only on
successful fault
recovery
7.4 Device Functional Modes
7.4.1 Power-Up and Operating States Hardware Configuration for VREG/VREF
Hardware configuration is not required. Voltage regulator voltage (3.3 or 5 V or disabled) is based on orderable
part number.
7.4.1.1 POWER Up
During power-up, all internal circuits are enabled. The VREG will also be enabled based on the hardware
configuration (see Voltage Regulator Control (address = 0xB) section). All gate drive outputs are held low and
the nFAULT pin is taken low by the IC while power up is being executed.
7.4.1.2 STANDBY State
After the startup sequence is completed and the PVDD voltage is above V_{PVDD_UVLO2}, the DRV8305 will indicate
successful and fault-free power up of all circuits by releasing the nFAULT pin.
The device will also enter STANDBY state any time that EN_GATE is taken low or a latched fault occurs.
Gate driver always has control of the power FETs even in STANDBY state.
TI recommends to set up the device control registers through SPI in the STANDBY state.
7.4.1.3 OPERATING State
Normal operation of the gate driver and current shunt amplifiers can be initiated by taking EN_GATE from a low
state to a high state. In this state the charge pump is powered up and the driver is ready for operation.
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