TL16C750 Datasheet, PDF (33/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Driver
External
XIN
Clock
Optional
Clock
Output
Optional
Driver
XOUT
VCC
C1
RP
Oscillator Clock
to Baud Generator
Logic
C2
XIN
Crystal
RX2
XOUT
VCC
Oscillator Clock
to Baud Generator
Logic
CRYSTAL
3.072 MHz
1.8432 MHz
TYPICAL CRYSTAL/ OSCILLATOR NETWORK
RP
1 MΩ
RX2
1.5 kΩ
C1
10 – 30 pF
1 MΩ
1.5 kΩ
10 – 30 pF
C2
40 – 60 pF
40 – 60 pF
Figure 21. Typical Clock Circuits
receiver buffer register (RBR)
The ACE receiver section consists of a RSR and a RBR. The RBR is actually a 64-byte FIFO. Timing is supplied
by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register.
The ACE RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into
the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available
interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
scratch register
The scratch register is an 8-bit register used by the programmer as a scratchpad that temporarily holds the
programmer data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
64-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at the SOUT terminal. In the TL16C450 mode, when the THR is empty
and the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
33