TL16C750 Datasheet, PDF (23/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
accessible registers
The system programmer, through the CPU, has access to and control over any of the ACE registers. These
registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in
Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0
2
2
3
4
Receiver
Bit
Buffer
No. _Register
(Read
Only)
RBR
Transmitter
Holding
Register
(Write
Only)
THR
Interrupt
Enable
Register
IER
Interrupt
Ident.
Register
(Read
Only)
IIR
FIFO
Control
Register
(Write
Only)
FCR
Line
Control
Register
LCR
Modem
Control
Register
MCR
0 Data Bit 0† Data Bit 0
1
Data Bit 1
Data Bit 1
Enable
Received
Data
Available
Interrupt
(ERBI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
0 when
interrupt
Pending
Interrupt
ID
Bit 1
FIFO
Enable
Receiver
FIFO
Reset
Word
Length
Select
Bit 0
(WLS0)
Word
Length
Select
Bit 1
(WLS1)
Data
Terminal
Ready
(DTR)
Request
to Send
(RTS)
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
3
Data Bit 3
Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 2
(see
Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
4
Data Bit 4
Data Bit 4
Sleep Mode
0
Enable
Reserved
Even
Parity
Select
(EPS)
Loop
5
Data Bit 5
Data Bit 5
Low Power
Mode Enable
64 Byte
FIFO
Enabled
64 Byte
FIFO
Enable‡
Stick
Parity
Flow
Control
Enable
(AFE)
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(see
Note 11)
Receiver
Trigger
(LSB)
Break
Control
0
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(see
Note 11)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)‡
0
† _{Bit 0 is the least significant bit. It is the first bit serially transmitted or received.}
‡ _{Access to DLAB LSB, MSB, and FCR bit 5 require LCR bit 7 = 1}
NOTE 11: These bits are always 0 in the TL16C450 mode.
5
Line
Status
Register
LSR
Data
Ready
(DR)
6
7
0 DLAB = 1
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
MSR
SCR
DLL
Delta
Clear
to Send
Bit 0
Bit 0
(∆CTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(∆DSR)
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Framing
Error
(FE)
Break
Interrupt
(BI)
Transmitter
Holding
Register
(THRE)
Transmitter
Empty
(TEMT)
Error in
Receiver
FIFO
(see
Note 12)
Delta
Data
Carrier
Detect
(∆DCD)
Clear
to
Send
(CTS)
Data
Set
Ready
(DSR)
Ring
Indicator
(RI)
Data
Carrier
Detect
(DCD)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1 DLAB = 1
Latch
(MSB)
DLM
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
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