TL16C750 Datasheet, PDF (11/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
commercial maximum switching characteristics, V_CC = 4.75 V, T_J = 115°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
INTRINSIC
DELAY
(ns)
DELTA
DELAY
(ns/pF)
CL = 15 pF
DELAY (ns)
CL = 50 pF CL = 85 pF
tPLH
tPHL
tr
tf
– 0.92
0.571
7.65
27.66
47.66
XIN
XO
– 0.79
0.312
3.89
14.83
25.76
Output rise time, XO
10.86
40.42
69.98
Output fall time, XO
5.47
20.90
36.34
CL = 100 pF
56.23
30.45
82.65
42.95
commercial maximum switching characteristics, V_CC = 3 V, T_J = 115°C
PARAMETER
tPLH
tPHL
tr
tf
FROM
(INPUT)
XIN
TO
(OUTPUT)
INTRINSIC
DELAY
(ns)
– 4.69
XO
– 3.05
Output rise time, XO
Output fall time, XO
DELTA
DELAY
(ns/pF)
1.017
0.442
CL = 15 pF
10.57
3.58
14.39
5.06
DELAY (ns)
CL = 50 pF
46.16
19.04
64.87
26.53
CL = 85 pF
81.75
34.51
115.35
48.01
CL = 100 pF
97.00
41.13
136.98
57.21
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 10)
PARAMETER
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
td12
Delay time, RCLK to sample clock
Delay time, stop to set receiver error inter-
td13
rupt or read RBR to LSI interrupt or stop to
RXRDY↓
tSCD
tSINT
7
7, 8, 9,
10, 11
10 ns
2
RCLK
cycle
td14
Delay time, read RBR/LSR low to reset
interrupt low
tRINT
7, 8, 9,
10, 11
CL = 75 pF
120 ns
NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER†
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
td15 Delay time, INTRPT to transmit start
tIRS
12
8
24
baudout
cycles
td16 Delay time, start to interrupt
tSTI
12
8
10
baudout
cycles
td17 Delay time, WR THR to reset interrupt
tHR
12
CL = 75 pF
50 ns
td18 Delay time, initial write to interrupt (THRE)
tSI
12
16
34
baudout
cycles
td19 Delay time, read IIR to reset interrupt (THRE)
td20 Delay time, write to TXRDY inactive
tIR
tWXI
12
13, 14
td21 Delay time, start to TXRDY active
tSXA
13, 14
† _{THRE = transmitter holding register empty, IIR = interrupt identification register.}
CL = 75 pF
CL = 75 pF
CL = 75 pF
70 ns
75 ns
9
baudout
cycles
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