TL16C750 Datasheet, PDF (22/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB† A2
A1
A0
REGISTER
0
L
L
L Receiver buffer (read), transmitter holding register (write)
0
L
L
H Interrupt enable register
X
L
H
L Interrupt identification register (read only)
X
L
H
L FIFO control register (write)
X
L
H
H Line control register
X
H
L
L Modem control register
X
H
L
H Line status register
X
H
H
L Modem status register
X
H
H
H Scratch register
1
L
L
L Divisor latch (LSB)
1
L
L
H Divisor latch (MSB)
† _{The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal}
is controlled by writing to this bit location (see Table 3).
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2
RTS
DTR
OUT1
Scratch Register
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Registers
Receiver FIFO
XMIT FIFO
Table 2. ACE Reset Functions
RESET
CONTROL
RESET STATE
Master Reset
All bits cleared (0 – 5 forced and 6 – 7 permanent)
Master Reset
Bit 0 is set, bits 1 – 4 are cleared, and bits 5 – 7 are cleared
Master Reset
All bits cleared
Master Reset
All bits cleared
Master Reset
All bits cleared (6 – 7 permanent)
Master Reset
Bits 5 and 6 are set, all other bits are cleared
Master Reset
Bits 0 – 3 are cleared, bits 4 – 7 are input signals
Master Reset
High
Read LSR/MR
Low
Read RBR/MR
Low
Read IR/Write THR/MR Low
Read MSR/MR
Low
Master Reset
High
Master Reset
High
Master Reset
High
Master Reset
High
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
Master Reset
No effect
MR/FCR1 – FCR0/
∆FCR0
All bits cleared
MR/FCR2 – FCR0/
∆FCR0
All bits cleared
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