TL16C750 Datasheet, PDF (16/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
SIN
Data Bits 5 – 8
Stop
Sample Clock
Trigger Level
INTRPT
(FCR6, 7 = 0, 0)
Line Status
INTRPT
(LSI)
RD1
(RD LSR)
td13
(see Note A)
50%
50%
50%
td14
50%
td14
Active
50%
RD1
(RD RBR)
NOTE A: For a time-out interrupt, td13 = 9 RCLKs.
Active
50%
Figure 8. Receive FIFO First Byte (Sets DR Bit) Waveforms
(FIFO at or above
trigger level)
(FIFO below
trigger level)
SIN
Sample Clock
Time-Out or
Trigger Level
INTRPT
Line Status
INTRPT (LSI)
RD1, RD2
(RD LSR)
Stop
td13
(see Note A)
50%
50%
td14
Top Byte of FIFO
50%
td13
td14
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RD1, RD2
(RD RBR)
Active 50%
Previous Byte
Read From FIFO
NOTE A: For a time-out interrupt, td13 = 9 RCLKs.
50%
Active
Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
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