TL16C750 Datasheet, PDF (26/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT signal in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table3 and are described in the following bulleted list.
D Bit 0: When set, this bit enables the received data available interrupt.
D Bit 1: When set, this bit enables the THRE interrupt.
D Bit 2: When set, this bit enables the receiver line status interrupt.
D Bit 3: When set, this bit enables the modem status interrupt.
D Bit 4: When set, this bit enables sleep mode. The ACE is always awake when there is a byte in the
transmitter, activity on the SIN, or when the device is in the loopback mode. The ACE is also awake when
either ∆CTS, ∆DSR, ∆DCD, or TERI = 1. Bit 4 must be set to enable sleep mode.
D Bit 5: When set, this bit enables low-power mode. Low-power mode functions similar to sleep mode.
However, this feature powers down the clock to the ACE only, while keeping the oscillator running. Bit 5 must
be set to enable low-power mode.
D Bits 6 and 7: Not used (always cleared)
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
D Priority 1 – Receiver line status (highest priority)
D Priority 2 – Receiver data ready or receiver character timeout
D Priority 3 – Transmitter holding register empty
D Priority 4 – Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Details on each bit are as follows:
D Bit 0: This bit can be used either in a hardwire prioritized, or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
D Bits 1 and 2: Used to identify the highest priority interrupt pending as indicated in Table 3.
D Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a time-out interrupt is pending.
D Bit 4: Not used (always cleared)
D Bits 5, 6, and 7: These bits are to verify the FIFO operation. When all 3 bits are cleared, TL16C450 mode
is chosen. When bits 6 and 7 are set and bit 5 is cleared, 16-byte mode is chosen. When bits 5, 6, and 7
are set, 64-byte mode is chosen.
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