TL16C750 Datasheet, PDF (24/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
D Bit 0: FCR0 when set enables the transmit and receive FIFOs. This bit must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
D Bit 1: FCR1 when set clears all bytes in the receiver FIFO and resets its counter. The RSR is not cleared.
The logic 1 that is written to this bit position is self clearing.
D Bit 2: FCR2 when set clears all bytes in the transmit FIFO and resets its counter to 0. The TSR is not
cleared. The logic 1 that is written to this bit position is self clearing.
D Bit 3: When FCR0 is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to
mode 1.
D Bit 4: Reserved for future use.
D Bit 5: When this bit is set 64-byte mode of operation is selected. When cleared, the 16-byte mode is
selected. A write to FCR bit 5 is protected by setting the line control register (LCR) bit 7 = 1. LCR bit 7 needs
to cleared for normal operation.
D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
BIT 7
0
0
1
1
Table 4. Receiver FIFO Trigger Level
BIT 6
0
1
0
1
16-BYTE RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
64-BYTE RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
16
32
56
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and as the
interrupt, is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06 or 0110h) has higher priority than the received data available (IIR
= 04) interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
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