TL16C750 Datasheet, PDF (28/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
BIT 2
WORD LENGTH SELECTED NUMBER OF STOP
BY BITS 1 AND 2
BITS GENERATED
0
Any word length
1
1
5 bits
1 1/2
1
6 bits
2
1
7 bits
2
1
8 bits
2
D Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in data transmitted between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit
3 is cleared, no parity is generated or checked.
D Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
D Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When
bit 5 is cleared, stick parity is disabled.
D Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (low) state. When bit 6 is cleared, the break condition is disabled and has no affect
on the transmitter logic; it only affects the serial output.
D Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write or access bit 5 of the FCR. Bit 7 must be cleared during a read or write
to access the receiver buffer, the THR, or the IER.
line status register (LSR)^†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are described in the following bulleted list and summarized in Table 3.
D Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set when a complete incoming character
is received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR
or the FIFO.
D Bit 1^‡: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in
the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. When the FIFO mode data continues to fill the FIFO beyond
the trigger level, an OE occurs only after the FIFO is full and the next character has been completely
received in the shift register. An OE is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
D Bit 2^‡: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, PE is associated with the particular character in the FIFO to
which it applies. PE is revealed to the CPU when its associated character is at the top of the FIFO.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.}
‡ _{Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.}
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