TL16C750 Datasheet, PDF (30/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
D Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP
is set, the following occurs:
– SOUT is asserted high.
– SIN is disconnected.
– The output of the TSR is looped back into the RSR input.
– The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to their inactive (high) states.
D Bit 5: This bit (AFE) is the autoflow control enable. When bit 5 is set, the autoflow control, as described in
the detailed description, is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
MCR BIT 5
(AFE)
1
1
0
MCR BIT 1
(RTS)
1
0
X
ACE FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
Auto-RTS and auto-CTS disabled
When bit 5 of the FCR is cleared, there is a 16-byte AFC. When bit 5 of the FCR is set, there is a 64-byte AFC.
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information. When a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
D Bit 0: This bit is the change in clear-to-send (∆ CTS) indicator. ∆ CTS indicates that CTS has changed states
since the last time it was read by the CPU. When ∆ CTS is set (autoflow control is not enabled and the
modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled, no interrupt is generated. When ∆CTS is set, sleep or low-power modes are avoided.
D Bit 1: This bit is the change in data set ready (∆ DSR) indicator. ∆ DSR indicates that DSR has changed
states since the last time it was read by the CPU. When ∆ DSR is set and the modem status interrupt is
enabled, a modem status interrupt is generated. When ∆DSR is set, the sleep or low-power modes are
avoided.
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