TL16C750 Datasheet, PDF (17/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)
SIN
(first byte)
Stop
50%
Active
See Note A
Sample Clock
td13
(see Note B)
RXRDY
50%
td14
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, td13 = 9 RCLKs.
Figure 10. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
RD
(RD RBR)
SIN
(first byte that reaches
the trigger level)
Sample Clock
td13
(see Note B)
RXRDY
50%
50%
Active
See Note A
td14
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, td13 = 9 RCLKs.
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
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