TL16C750 Datasheet, PDF (3/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

functional block diagram
S
e
Internal ⁸
Data Bus
l
e
c
t
9–2
D(7 – 0)
Data
Bus
Buffer
8
Receiver
Buffer
Register
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
Receiver
FIFO
Receiver
Shift
Register
11
SIN
31
A0
A1 ³⁰
A2 ²⁹
14
CS0
CS1 ¹⁵
16
CS2
ADS ²⁸
MR ³⁹
24
RD1
RD2 ²⁵
WR1 ²⁰
21
WR2
26
DDIS
TXRDY ²⁷
XIN ¹⁸
XOUT ¹⁹
RXRDY ³²
Select
and
Control
Logic
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Transmitter
S
FIFO
e
l
8
e
c
t
8
8
VCC ⁴⁴
VSS ²²
Power
Supply
Interrupt
Enable
Register
8 ^Interrupt
Control
Logic
Interrupt
8
Identification
Register
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the FN package.
Receiver
Timing and
Control
Transmitter
Timing and
Control
8 ^Transmitter
Shift
Register
Modem
Control
Logic
10
RCLK
36
RTS
17 _BAUDOUT
Autoflow
Control
Enable
(AFE)
13
SOUT
40
CTS
37
DTR
41
DSR
42 _DCD
43
RI
38
OUT1
35
OUT2
33 _INTRPT
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