TL16C750 Datasheet, PDF (29/35 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
line status register (LSR)^† (continued)
D Bit 3^‡: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character
does not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. FE is
revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize
after a FE. To accomplish this, it is assumed that the FE is due to the next start bit. The ACE samples this
start bit twice and then accepts the input data.
D Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input
was held in the low state for longer than a full-word transmission time. A full-word transmission time is
defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU
reads the contents of the LSR. In the FIFO mode, BI is associated with the particular character in the FIFO
to which it applies. BI is revealed to the CPU when its associated character is at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after
SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
D Bit 5: This bit is the transmitter holding register empty (THRE) indicator. THRE is set when the THR is
empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when
THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the
TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set
when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
D Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and TSR are both empty.
D Bit 7: In TL16C750 mode and in TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is
set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the
microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
D Bit 0: This bit (DTR) controls the DTR output.
D Bit 1: This bit (RTS) controls RTS output.
D Bit 2: This bit (OUT1) controls OUT1 signal.
D Bit 3: This bit (OUT2) controls the OUT2 signal.
When any of bits 0 through 3 is set, the associated output is forced low; a cleared bit forces the associated output
high.
† _{The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.}
‡ _{Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.}
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