VS6724 Datasheet, PDF (97/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Programming model and register description
Table 47. Output control (continued)
Index
OutputControl⁽¹⁾
bPClkSetup
0x23b0
Default value
Type
flag bits
0x05
CODED
[0] PClkSetup_prog_lo
1-> Rising Edge of PCLK
0-> Falling Edge of PCLK
[1] PClkSetup_prog_hi
1-> Polarity of PLCK normally high
0-> Polarity of PLCK normally low
[2] PClkSetup_sync_en
1-> Enable PCLK during Embedded sync codes
0-> Disable PCLK during Embedded sync codes
[3] PClkSetup_hsync_en_n
1-> enable the PCLK outside the HSYNC active period
0-> disable the PCLK outside the HSYNC active period
[4] PClkSetup_hsync_en_n_track_internal
1-> use the internal tracked hsync for the qualification of the bit[3]
0-> use the manually set hsync for the qualification of the bit[3]
[5] PClkSetup_vsync_n
1-> enable pclk outside VSYNC active period
0-> disable pclk outside VSYNC active period
[6] PClkSetup_vsync_n_track_internal
1-> use the internal tracked vsync for the qualification of the bit[5]
0-> use the manually set vsync for the qualification of the bit[5]
[7] PClkSetup_freer
1-> Set the PCLK to free run
0 ->Set the PCLK to be controlled
fPclkEn
0x23b2
Default value
Type
Possible values
<1> TRUE
Flag_e
<0> FALSE
<1> TRUE
1. Changes only consumed during a change to RUN mode
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