VS6724 Datasheet, PDF (29/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Functional description
2.9.2
Line / frame blanking data
The values which are output during line and frame blanking are an alternating pattern of
0x10 and 0x80 by default. These values may be changed by writing to the BlankData_MSB
and BlankData_LSB registers in the Dither control bank.
2.9.3
YCbCr 4:2:2 data format
YCbCr 422 data format requires 4 bytes of data to represent 2 adjacent pixels. ITU601-656
defines the order of the Y, Cb and Cr components as shown in Figure 13.
Figure 13. Standard Y Cb Cr data order
HSYNC SIGNAL
EAV Code START OF DIGITAL ACTIVE LINE
81
00
F00X
F00Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
4-data
packet
The VS6724 bYCbCrSetup register can be programmed to change the order of the
components as follows:
Figure 14. Y Cb Cr data swapping options register bYCbCrSetup
Components order
in 4-byte data packet
1st
2nd
3rd
4th
1
1
Y
Cb
Y
Cr
DEFAULT
0
1
Cb
Y
Cr
Y
1
0
Y
Cr
Y
Cb
0
0
Cr
Y
Cb
Y
2.9.4
YCbCr 4:0:0
The ITU protocol allows the encapsulation of various data formats over the link. The
following data formats are also proposed encapsulated in ITU601-656 protocol:
● YCbCr 4:0:0 - luminance data channel
This is done as described in Figure 15. In this output mode the output data per pixel is a
single byte. Therefore the output PCLK and data rate is halved.
It is possible to reverse the overall bit order of the component through a register
programming.
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