VS6724 Datasheet, PDF (50/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

Programming model and register description
4
Programming model and register description
VS6724
4.1
Programming model
The VS6724 addressable register/memory space is configured as shown below. It consists
of four principal areas each of which provides a different function:
User Interface: this area starting from address zero provides the user interface. Register
reads and writes to this block are passed through the internal micro and processed. All
operational control of the device by the host should be performed through these user
interface locations.Many of these registers are detailed in Section 4.2: Register description.
Registers not listed in this datasheet should be considered as reserved or read-only and
should NOT be written to, as this may cause unpredictable results.
Hardware registers: provides direct access to hardware registers associated with each
functional block of the device. In normal operation, these registers will be accessed under
the control of the micro. i.e. they should never be accessed by the host system. However,
they may be directly accessed by the host for debug and test purposes.
XDATA RAM: provides temporary variable storage for the on-board micro.
Patch RAM: provides memory space to download firmware patches and modify device
operation. This provides a software update mechanism without the need for a new program
ROM.
Figure 39. System / Host view of VS6724 memory
FFFF
D800
C000
HARDWARE REGISTERS
9FFF
9000
8FFF
8000
4K MCU PATCH RAM
4K MCU XDATA RAM
USER INTERFACE
LEGEND
User Interface
Hardware Registers
XDATA/Patch RAM
Blank space
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0000