VS6724 Datasheet, PDF (43/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Host communication - I²C control interface
b) When a read is performed master acknowledges data.
Repeat 4 and 5 until all the required data has been written or read.
Minimum number of data bytes for a read =1 (Shortest Message length is 2-bytes).
The master outputs a negative acknowledge for the data when reading the last byte of data.
This causes the slave to stop the output of data and allows the master to generate a STOP
condition.
6. Master generates a STOP condition or a repeated START.
Figure 28. Device addresses
Sensor address
0
0
1
0
0
0
0 R/W
Sensor write address 20_H
0
0
1
0
0
0
0
0
Sensor read address 21_H
0
0
1
0
0
0
0
1
3.2.1
Data valid
The data on SDA is stable during the high period of SCL. The state of SDA is changed
during the low phase of SCL. The only exceptions to this are the start (S) and stop (P)
conditions as defined below. (See I²C slave interface for full timing specification).
Figure 29. SDA data valid
SDA
SCL
Data line
stable
Data valid
Data change
Data line
stable
Data valid
3.2.2
Start (S) and Stop (P) conditions
A START (S) condition defines the start of a V2W message. It consists of a high to low
transition on SDA while SCL is high.
A STOP (P) condition defines the end of a V2W message. It consists of a low to high
transition on SDA while SCL is high.
After STOP condition the bus is considered free for use by other devices. If a repeated
START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated
START (Sr) are considered to be functionally equivalent.
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