VS6724 Datasheet, PDF (44/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

Host communication - I²C control interface
Figure 30. START and STOP conditions
SDA
VS6724
3.2.3
3.2.4
SCL
S
START
condition
P
STOP
condition
Acknowledge
After every byte transferred the receiver must output an acknowledge bit. To acknowledge
the data byte receiver pulls SDA during the 9th SCL clock cycle generated by the master. If
SDA is not pulled low then the transmitter stops the output of data and releases control of
the bus back to the master so that it can either generate a STOP or a repeated START
condition.
Figure 31. Data acknowledge
SDA data
output by
transmitter
SDA data
output by
receiver
Negative acknowledge (A)
SCL clock
from master
S
Acknowledge (A)
1
2
8
9
START condition
Clock pulse for acknowledge
Index space
Communication using the serial bus centres around a number of registers internal to the
either the sensor or the co-processor. These registers store sensor status, set-up, exposure
and system information. Most of the registers are read/write allowing the receiving
equipment to change their contents. Others (such as the chip id) are read only.
The internal register locations are organized in a 64k by 8-bit wide space. This space
includes “real” registers, SRAM, ROM and/or micro controller values.
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