VS6724 Datasheet, PDF (10/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

Functional description
2
Functional description
VS6724
The VS6724 simplified block diagram is shown in Figure 1, with the following main blocks:
● UXGA-sized pixel array
● Video pipe
● Statistics gathering unit
● Clock generator
● Microprocessor
● Video timing generator
Figure 1. Simplified block diagram
Clock
CLK
Generator
I²C Interface
I²C
SDA
SCL
CE
VDD
GND
RESET
VREG
Video Timing
Generator
Microprocessor
Statistics
Gathering
AVDD
GND
UXGA
Pixel
Array
Video
Engine
Video
Compressor
(JPEG
engine)
Output
Coder
Bypass
Bypass
Bypass
FSO
VSYNC
HSYNC
PCLK
D[0:7]
2.1
Operation
A video timing generator controls a UXGA-sized pixel array to produce raw Bayer images.
The analogue pixel information is digitized and passed into the video pipe. The video pipe
contains a number of different functions (explained in detail later). At the end of the video
pipe, data is output to the host system over an 8-bit parallel interface along with qualification
signals.
The whole system is controlled by an embedded microprocessor that is running firmware
stored in an internal ROM. The external host communicates with this microprocessor over
an I²C interface. The microprocessor does not handle the video data itself but is able to
control all the functions within the video pipe. Real-time information about the video data is
gathered by a statistics engine and is available to the microprocessor. The processor uses
this information to perform real-time image control tasks such as automatic exposure
control.
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