VS6724 Datasheet, PDF (42/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

Host communication - I²C control interface
VS6724
read. A read message is terminated by the bus master generating a negative acknowledge
after reading a final byte of data.
A message can only be terminated by the bus master, either by issuing a stop condition, a
repeated start condition or by a negative acknowledge after reading a complete byte during
a read operation.
3.2
Detailed overview of the message format
Figure 27. Detailed overview of message format
1
2
3
4
5
6
S
(Sr)
7-bit device
address
R/W A
8-bit Data
AP
(A) (Sr)
SDA
SCL
S
or
Sr
MSB
1
2
LSB
MSB
7
8
9
1
2
P
LSB
Sr
Sr
7
8
9
or
P
START
or
repeated
START
condition
Device address
R/W
Bit
0 - Write
1 - Read
ACK
signal
from
slave
Data byte from
transmitter
R/W=0 - Master
R/W=1 - Slave
ACK
signal
from
receiver
STOP
or
repeated
Start
condition
The V2W generic message format consists of the following sequence:
1. Master generates a START condition to signal the start of new message.
2. Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to
communicate with followed by a R/W bit.
a) R/W = 0 then the master (transmitter) is writing to the slave (receiver).
b) R/W = 1 the master (receiver) is reading from the slave (transmitter).
3. The addressed slave acknowledges the device address.
4. Data transmitted on the bus
a) When a write is performed then master outputs 8-bits of data on SDA (MS Bit
first).
b) When a read is performed then slave outputs 8-bits of data on SDA (MS Bit First).
5. Data receive acknowledge
a) When a write is performed slave acknowledges data.
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