VS6724 Datasheet, PDF (33/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Functional description
2.10.2
Prevention of false synchronization codes
The VS6724 is able to prevent the output of 0xFF and/or 0x00 data from being
misinterpreted by a host system as the start of synchronization data. This function is
controlled the bCodeCheckEnable register.
Mode 1 (ITU656 compatible)
The structure of an image frame with ITU656 codes is shown in Figure 18.
Figure 18. ITU656 frame structure with even codes
Line 1
SAV
80
Frame of image data
EAV
9D
Line 480
SAV
AB
Frame blanking period
EAV
B6
The synchronization codes for odd and even frames are listed in Table 3 and Table 4. By
default all frames output from the VS6724 are EVEN. It is possible to set all frames to be
ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in
theDither control register bank.
Table 3. ITU656 embedded synchronization code definition (even frames)
Name
Description
4-byte sequence
SAV
EAV
SAV (blanking)
EAV (blanking)
Line start - active
Line end - active
Line start - blanking
Line end - blanking
FF 00 00 80
FF 00 00 9D
FF 00 00 AB
FF 00 00 B6
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