VS6724 Datasheet, PDF (37/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Figure 22. VSYNC timing example
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Functional description
V=0
V=1
vsync
V=0
V=1
2.10.5
If manual mode is selected then the line number for VSYNC rising edge and falling edge is
programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLine
registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel
registers. Similarly the line count for the falling edge position is specified in the
bVsyncFallingLine registers, and the pixel count is specified in the bVsyncFallingPixel
registers.
Pixel clock (PCLK)
The PCLK signal is controlled by the Dither control register. The following options are
available:
● enable/disable
● select polarity
● select starting phase
● qualify/don’t qualify embedded synchronization codes
● enable/disable during horizontal blanking
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