VS6724 Datasheet, PDF (21/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Functional description
2.6.5
Note:
JPEG output as a conventional frame
To keep compatibility with conventional frame format, the JPEG frame is output in a series of
packets targeted to look like image lines. The Hsync envelopes each packet (line) of data
and the Vsync envelopes the complete frame. The start of the frame is indicated by a
transition of the Vsync and Hsync. This will occur when the output FIFO has accumulated
enough JPEG data for the first line (default line size 512 = 1KBytes). When this line is
output, it will then output blocks of blank data (16Byte blocks) until the next 512Bytes of data
is available.
The number of bytes per line can be programmed using the following registers, both 16 bit
registers should be programmed with the same value:
● wLineLength {MSB 0x2511, LSB 0x2512} default = 512
● wThres {MSB 0x251b, LSB 0x251c}
The number of PCLKs in a line is equal to 2 x the line length and the maximum line length is
2K.
In most cases the JPEG data will not fill the last line of data and padding data is added after
the JPEG end of image marker FFD9h filling the remainder of the last line. Note that it is
possible that the JPEG data will exactly fill the line and no padding is required.
The value of padding bytes can be programmed using the following registers, both registers
should be programmed with the same value;
● bJPEG_FILL_VAL {0x23b4} default = 0xA5
● bJPEG_PADDING {0x23b6}
It is not possible to control the timing of the Vsync and Hsync signals in JPEG mode. You
can however change the polarity of the signals and select if the Hsync is present or not
during the interframe period.
PCLK can be made to be present only during active JPEG data, and therefore not present
during the interline or interframe periods. The rising edge of PCLK is always half clock
delayed from both Hsync and Vsync.
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