VS6724 Datasheet, PDF (111/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

VS6724
Electrical characteristics
6.7
Parallel data interface timing
VS6724 contains a parallel data output port (D[7:0]) and associated qualification signals
(HSYNC, VSYNC, PCLK and FSO).
This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or
bit-serial output configurations. The port is disabled (high impedance) upon reset.
Figure 43. Parallel data output video timing
1/f_PCLK
t_PCLKL
t_PCLKH
PCLK
polarity = 0
D[0:7]
HSYNC,
VSYNC
t_DV
Valid
Table 62. Parallel data interface timings
Symbol
Description
Min.
f_PCLK
t_PCLKL
t_PCLKH
t_DV
PCLK frequency
PCLK low width
PCLK high width
PCLK to output valid
(1/2 * (1/fPCLK)) -1
(1/2 * (1/fPCLK)) -1
-1
Max.
80
(1/2 * (1/fPCLK)) +1
(1/2 * (1/fPCLK)) +1
1
Unit
MHz
ns
ns
ns
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