VS6724 Datasheet, PDF (38/118 Pages) STMicroelectronics – 2 Megapixel single-chip camera module

Functional description
VS6724
Figure 23. QCLK options
data
D0
D1
D2
Negative edge
PCLK
Positive edge
Negative edge
Positive edge
None-active
level - High
None-active
level - Low
The YCbCr, RGB and Bayer timings are represented on Figure 24, with the associated
qualifying PCLK clock. The output clock rate is effectively halved for the Bayer 8-bit and
YCbCr4:0:0 modes where only one byte of output data is required per pixel.
Figure 24. Qualification clock
16-bit data output formats - 2 bytes per pixel
Data[7:0]
Cb_n,n+1
Y_n
YCbCr
PCLK
Cr_n,n+1
Data[7:0]
RGB565
RGB444
PCLK
Pix0_lsb
Pix0_msb
Pix1_lsb
Bayer 10-Bit ^Data[7:0]
PCLK
Pix0_lsb
Pix0_msb
Pix1_lsb
8-bit data output formats- 1 byte per pixel
Y_n+1
Cb_n+2,n+3
Pix1_msb
Pix2_lsb
Pix1_msb
Pix2_lsb
Data[7:0]
Bayer 8-Bit
Pix0
PCLK
Pix1
Pix2
Data[7:0]
YCbCr 4:0:0
Pix0
PCLK
Pix1
Pix2
In practice the user is likely to require to write some additional setup information prior to
receive the required data output.
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