UPSD3212C Datasheet, PDF(40/152 Page) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

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UPSD3212C Datasheet, PDF (40/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

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UPSD3212C, UPSD3212CV

USART Interrupt

â The USART Interrupt is generated by RI (Re-

ceive Interrupt) OR TI (Transmit Interrupt).

â When the USART Interrupt is generated, the

corresponding request flag must be cleared by

the software. The interrupt service routine will

have to check the various USART registers to

determine the source and clear the correspond-

ing flag.

â Both USARTâs are identical, except for the addi-

tional interrupt controls in the Bit 4 of the addi-

tional interrupt control registers (A7H, B7H).

Interrupt Priority Structure

Each interrupt source can be assigned one of two

priority levels. Interrupt priority levels are defined

by the interrupt priority special function register IP

and IPA.

0 = low priority

1 = high priority

Table 18. Priority Levels

Source

Int0

2nd USART

Timer 0

IÂ²C

Int1

reserved

Timer 1

reserved

1st USART

Timer 2+EXF2

A low priority interrupt may be interrupted by a

high priority interrupt level interrupt. A high priority

interrupt routine cannot be interrupted by any oth-

er interrupt source. If two interrupts of different pri-

ority occur simultaneously, the high priority level

request is serviced. If requests of the same priority

are received simultaneously, an internal polling

sequence determines which request is serviced.

Thus, within each priority level, there is a second

priority structure determined by the polling se-

quence.

Interrupts Enable Structure

Each interrupt source can be individually enabled

or disabled by setting or clearing a bit in the inter-

rupt enable special function register IE and IEA. All

interrupt source can also be globally disabled by

the clearing Bit EA in IE (see Table 19). Please

see Tables 20, 21, 22, and 23 for individual bit de-

scriptions.

Priority with Level

0 (highest)

9 (lowest)

Table 19. SFR Register

SFR Reg

Addr Name

A7 IEA

B7 IPA

Bit Register Name

ES2

EI2C

ET2

ET1 EX1 ET0

PS2

PI2C

PT2

PT1 PX1 PT0

Reset

Value

Comments

Interrupt

Enable (2nd)

EX0

Interrupt

Enable

Interrupt

Priority (2nd)

PX0

Interrupt

Priority

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