UPSD3212C Datasheet, PDF (129/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Table 92. External Program Memory AC Characteristics (with the 3V MCU Module)
Symbol
Parameter⁽¹⁾
24MHz Oscillator
Min
Max
Variable Oscillator
1/t_CLCL = 8 to 24MHz
Unit
Min
Max
t_LHLL
ALE pulse width
43
2t_CLCL – 40
ns
t_AVLL
Address set up to ALE
17
t_CLCL – 25
ns
t_LLAX
Address hold after ALE
17
t_CLCL – 25
ns
t_LLIV
ALE Low to valid instruction in
80
4t_CLCL – 87 ns
t_LLPL
ALE to PSEN
22
t_CLCL – 20
ns
t_PLPH
PSEN pulse width
95
3t_CLCL – 30
ns
t_PLIV
PSEN to valid instruction in
60
3t_CLCL – 65 ns
t_PXIX
Input instruction hold after PSEN
0
0
ns
t_PXIZ(2) Input instruction float after PSEN
32
t_CLCL – 10 ns
t_PXAV(2) Address valid after PSEN
37
t_CLCL – 5
ns
t_AVIV
Address to valid instruction in
148
5t_CLCL – 60 ns
t_AZPL
Address float to PSEN
–10
–10
ns
Note: 1. Conditions (in addition to those in Table 87, V_CC = 3.0 to 3.6V): V_SS = 0V; C_L for Port 0, ALE and PSEN output is 100pF, for 5V
devices, and 50pF for 3V devices; C_L for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)
2. Interfacing the uPSD321X Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause
any damage to Port 0 drivers.
Table 93. External Clock Drive (with the 5V MCU Module)
Symbol
Parameter⁽¹⁾
40MHz Oscillator
Min
Max
Variable Oscillator
1/t_CLCL = 24 to 40MHz
Unit
Min
Max
t_RLRH
Oscillator period
25
41.7
ns
t_WLWH High time
10
t_CLCL – t_CLCX ns
t_LLAX2 Low time
10
t_CLCL – t_CLCX ns
t_RHDX Rise time
10
ns
t_RHDX Fall time
10
ns
Note: 1. Conditions (in addition to those in Table 86, VCC = 4.5 to 5.5V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for
other outputs is 80pF
Table 94. External Clock Drive (with the 3V MCU Module)
Symbol
Parameter⁽¹⁾
24MHz Oscillator
Min
Max
Variable Oscillator
1/t_CLCL = 8 to 24MHz
Unit
Min
Max
t_RLRH Oscillator period
41.7
125
ns
t_WLWH High time
12
t_CLCL – t_CLCX ns
t_LLAX2 Low time
12
t_CLCL – t_CLCX ns
t_RHDX
Rise time
12
ns
t_RHDX
Fall time
12
ns
Note: 1. Conditions (in addition to those in Table 87, V_CC = 3.0 to 3.6V): V_SS = 0V; C_L for Port 0, ALE and PSEN output is 100pF, for 5V
devices, and 50pF for 3V devices; C_L for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)
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