UPSD3212C Datasheet, PDF (142/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Figure 75. Reset (RESET) Timing
V_CC
RESET
V_CC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
Warm Reset
tOPR
AI07437
Table 112. Reset (RESET) Timing (5V Devices)
Symbol
Parameter
Conditions
t_NLNH
RESET Active Low Time⁽¹⁾
t_NLNH–PO
Power-on Reset Active Low Time
t_OPR
RESET High to Operational Device
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 113. Reset (RESET) Timing (3V Devices)
Symbol
Parameter
Conditions
t_NLNH
RESET Active Low Time⁽¹⁾
t_NLNH–PO
Power-on Reset Active Low Time
t_OPR
RESET High to Operational Device
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Table 114. V_STBYON Definitions Timing (5V Devices)
Symbol
Parameter
Conditions
t_BVBH
V_STBY Detection to V_STBYON Output High
(Note 1)
t_BXBL
V_STBY Off Detection to V_STBYON Output
Low
(Note 1)
Note: 1. V_STBYON timing is measured at V_CC ramp rate of 2ms.
Table 115. V_STBYON Timing (3V Devices)
Symbol
Parameter
t_BVBH
V_STBY Detection to V_STBYON Output High
t_BXBL
V_STBY Off Detection to V_STBYON Output
Low
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
Conditions
(Note 1)
(Note 1)
Min
Max
Unit
150
ns
1
ms
120
ns
Min
Max
Unit
300
ns
1
ms
300
ns
Min
Typ
Max Unit
20
µs
20
µs
Min
Typ
Max Unit
20
µs
20
µs
142/152