UPSD3212C Datasheet, PDF (140/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Figure 73. Peripheral I/O READ Timing
ALE
A/D BUS
CSI
RD
ADDRESS
tAVQV ( PA)
tSLQV ( PA)
tRLQV (PA)
DATA VALID
tRHQZ (PA)
tDVQV (PA)
DATA ON PORT A
Table 108. Port A Peripheral Data Mode READ Timing (5V Devices)
Symbol
Parameter
Conditions
Min
t_AVQV–PA
Address Valid to Data
Valid
t_SLQV–PA
CSI Valid to Data Valid
t_RLQV–PA
RD to Data Valid
t_DVQV–PA
Data In to Data Out Valid
t_RHQZ–PA
RD to Data High-Z
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
(Note 1)
(Note 2)
Table 109. Port A Peripheral Data Mode READ Timing (3V Devices)
Symbol
Parameter
Conditions
Min
t_AVQV–PA
Address Valid to Data Valid
t_SLQV–PA
CSI Valid to Data Valid
t_RLQV–PA
RD to Data Valid
t_DVQV–PA
Data In to Data Out Valid
t_RHQZ–PA
RD to Data High-Z
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
(Note 1)
(Note 2)
AI06610
Max
Turbo
Off
Unit
37
+ 10 ns
27
+ 10 ns
32
ns
22
ns
23
ns
Max
Turbo
Off
Unit
50
+ 20 ns
37
+ 20 ns
45
ns
38
ns
36
ns
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