UPSD3212C Datasheet, PDF (110/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 56):
s MCU I/O Mode
s CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
s CPLD Input – via the Input Macrocells (IMC)
s In-System Programming (ISP) – JTAG pins
(TMS, TCK, TDI, TDO) are dedicated pins for
device programming. (See the section entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE,” page 118, for
more information on JTAG programming.)
s Open Drain – Port C pins can be configured in
Open Drain Mode
s Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
Standby (V_STBY).
PC4 can be configured as a Battery-on Indicator
(V_BATON), indicating when V_CC is less than
V_BAT.
Port C does not support Address Out Mode, and
therefore no Control Register is required.
Figure 56. Port C Structure
DATA OUT
REG.
DQ
WR
MCELLBC[ 7:0]
READ MUX
P
D
B
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
DATA OUT
1
SPECIAL FUNCTION
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
ENABLE OUT
INPUT
MACROCELL
1
SPECIAL FUNCTION
PORT C PIN
CONFIGURATION
BIT
AI06618
Note: 1. ISP or battery back-up
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