UPSD3212C Datasheet, PDF (136/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Figure 70. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
Figure 71. Asynchronous Clock Mode Timing (product term clock)
tCHA
tCLA
CLOCK
INPUT
REGISTERED
OUTPUT
tSA tHA
tCOA
AI02864
AI02859
Table 102. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
38.4
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
62.5
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
71.4
t_SA
Input Setup Time
7
+2
t_HA
Input Hold Time
8
t_CHA
Clock Input High Time
9
t_CLA
Clock Input Low Time
9
t_COA
Clock to Output Delay
21
t_ARDA CPLD Array Delay
Any macrocell
11
+2
t_MINA
Minimum Clock Period
1/f_CNTA
16
Turbo
Off
+ 10
+ 10
+ 10
+ 10
Slew
Rate
–2
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
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