UPSD3212C Datasheet, PDF (125/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Symbol
Parameter
Test Condition
(in addition to those
Min.
Typ. Max.
Unit
in Table 86, page 122)
I_STBY
SRAM (PSD) Standby Current
(V_STBY input)
V_CC = 0V
0.5
1
µA
I_IDLE
SRAM (PSD) Idle Current
(V_STBY input)
V_CC > V_STBY
–0.1
0.1
µA
I_RST
Reset Pin Pull-up Current
(RESET)
V_IN = V_SS
–10
–55
µA
I_FR
XTAL Feedback Resistor
Current (XTAL1)
XTAL1 = V_CC
XTAL2 = V_SS
–20
–50
µA
I_LI
Input Leakage Current
V_SS < V_IN < V_CC
–1
1
µA
I_LO
Output Leakage Current
0.45 < V_OUT < V_CC
–10
10
µA
I_PD(1)
Power-down Mode
V_CC = 5.5V
LVD logic disabled
LVD logic enabled
250
µA
380
µA
Active (12MHz)
Idle (12MHz)
V_CC = 5V
20
30
mA
8
10
mA
Active (24MHz)
I_{CC_CPU(2,3,5)}
Idle (24MHz)
V_CC = 5V
30
38
mA
15
20
mA
Active (40MHz)
Idle (40MHz)
V_CC = 5V
40
62
mA
20
30
mA
PLD Only
I_{CC_PSD}
(DC)⁽⁵⁾
Operating
Supply Current
Flash
memory
PLD_TURBO = Off,
f = 0MHz⁽⁴⁾
PLD_TURBO = On,
f = 0MHz
During Flash memory
WRITE/Erase Only
Read only, f = 0MHz
0
µA/PT⁽⁵⁾
400
700
µA/PT
15
30
mA
0
0
mA
SRAM
f = 0MHz
0
0
mA
PLD AC Base
Note 4
I_{CC_PSD}
(AC)⁽⁵⁾
Flash memory AC Adder
SRAM AC Adder
2.5
3.5
1.5
3.0
mA/
MHz
mA/
MHz
Note: 1. I_PD (Power-down Mode) is measured with:
XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo Mode.
2. I_{CC_CPU} (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all
other pins are disconnected. I_CC would be slightly higher if a crystal oscillator is used (approximately 1mA).
3. I_{CC_CPU} (Idle Mode) is measured with:
XTAL1 driven with t_CLCH, t_CHCL = 5ns, V_IL = V_SS+0.5V, V_IH = V_CC– 0.5V, XTAL2 = not connected; Port 0 = V_CC;
RESET=V_CC; all other pins are disconnected.
4. See Figure 62 for the PLD current calculation.
5. I/O current = 0 mA, all I/O pins are disconnected.
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