UPSD3212C Datasheet, PDF (137/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Table 103. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
21.7
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
27.8
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
33.3
t_SA
Input Setup Time
10
+4
t_HA
Input Hold Time
12
t_CHA
Clock High Time
17
t_CLA
Clock Low Time
13
t_COA
Clock to Output Delay
36
t_ARD
CPLD Array Delay
Any macrocell
25
+4
t_MINA
Minimum Clock Period
1/f_CNTA
36
Turbo Slew
Off Rate
+ 20
+ 20
+ 20
+ 20 – 6
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
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