UPSD3212C Datasheet, PDF (109/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 55. The two ports can be
configured to perform one or more of the following
functions:
s MCU I/O Mode
s CPLD Output – Macrocells McellAB7-McellAB0
can be connected to Port A or Port B. McellBC7-
McellBC0 can be connected to Port B or Port C.
s CPLD Input – Via the Input Macrocells (IMC).
s Latched Address output – Provide latched
address output as per Table 71.
s Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be configured
to Open Drain Mode.
s Peripheral Mode – Port A only (80-pin package)
Figure 55. Port A and Port B Structure
WR
ADDRESS
ALE
DATA OUT
REG.
DQ
DQ
G
MACROCELL OUTPUTS
READ MUX
P
D
B
CONTROL REG.
DQ
WR
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
DATA OUT
ADDRESS
A[ 7:0]
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
ENABLE OUT
PORT
A OR B PIN
INPUT
MACROCELL
AI06605
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