UPSD3212C Datasheet, PDF (37/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
CSIOP
Addr Register Name
Offset
7
Bit Register Name
6
5
4
3
2
1
0
Reset
Value
Comments
21
Output
Macrocells BC
22
Mask Macrocells
AB
23
Mask Macrocells
BC
C0
Primary Flash
Protection
Sec3_ Sec2_ Sec1_ Sec0_
Prot Prot Prot Prot
Bit = 1 sector
is protected
C2
Secondary Flash Security
Protection
_Bit
*
*
*
*
*
Sec1_ Sec0_
Prot Prot
Security Bit =
1 device is
secured
B0
PMMR0
*
*
PLD
Mcells
clk
PLD
array-
clk
PLD
Turbo
*
APD
enable
*
Control PLD
00
power
consumption
B4
PMMR2
*
PLD PLD PLD PLD
array array array array *
Ale Cntl2 Cntl1 Cntl0
Blocking
*
00 inputs to PLD
array
E0
Page
00 Page Register
E2
VM
Periph-
mode
*
*
FL_ Boot_ FL_ Boot_ SR_
data data code code code
Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft)
* indicates bit is not used and need to set to '0.'
Configure
8032 Program
and Data
Space
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