UPSD3212C Datasheet, PDF (144/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Table 117. ISC Timing (3V Devices)
Symbol
Parameter
t_ISCCF Clock (TCK, PC1) Frequency (except for PLD)
t_ISCCH Clock (TCK, PC1) High Time (except for PLD)
t_ISCCL Clock (TCK, PC1) Low Time (except for PLD)
t_ISCCFP Clock (TCK, PC1) Frequency (PLD only)
t_ISCCHP Clock (TCK, PC1) High Time (PLD only)
t_ISCCLP Clock (TCK, PC1) Low Time (PLD only)
t_ISCPSU
t_ISCPH
t_ISCPCO
ISC Port Set Up Time
ISC Port Hold Up Time
ISC Port Clock to Output
t_ISCPZV ISC Port High-Impedance to Valid Output
t_ISCPVZ ISC Port Valid Output to High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Conditions
Min
(Note 1)
(Note 1)
40
(Note 1)
40
(Note 2)
(Note 2)
240
(Note 2)
240
12
5
Figure 77. MCU Module AC Measurement I/O Waveform
Max
Unit
12
MHz
ns
ns
2
MHz
ns
ns
ns
ns
30
ns
30
ns
30
ns
VCC – 0.5V
0.45V
0.2 VCC + 0.9V
Test Points
0.2 VCC – 0.1V
AI06650
Note: AC inputs during testing are driven at V_CC–0.5V for a logic '1,' and 0.45V for a logic '0.'
Timing measurements are made at V_IH(min) for a logic '1,' and V_IL(max) for a logic '0'
Figure 78. PSD MODULE AC Float I/O Waveform
VLOAD + 0.1V
VLOAD – 0.1V
0.2 VCC – 0.1V
Test Reference Points
VOH – 0.1V
VOL + 0.1V
AI06651
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to
float when a 100mV change from the loaded V_OH or V_OL level occurs
I_OL and I_OH ≥ 20mA
144/152