UPSD3212C Datasheet, PDF (134/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Figure 69. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 100. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
40.0
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
Maximum Frequency
Pipelined Data
1/(t_S+t_CO–10)
1/(t_CH+t_CL)
66.6
83.3
MHz
MHz
t_S
Input Setup Time
t_H
Input Hold Time
12
+ 2 + 10
ns
0
ns
t_CH
Clock High Time
t_CL
Clock Low Time
t_CO
Clock to Output Delay
Clock Input
6
Clock Input
6
Clock Input
13
ns
ns
– 2 ns
t_ARD
CPLD Array Delay
Any
macrocell
11
+2
ns
t_MIN
Minimum Clock Period⁽²⁾
t_CH+t_CL
12
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t_CLCL = t_CH + t_CL.
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