UPSD3212C Datasheet, PDF (138/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Figure 72. Input Macrocell Timing (product term clock)
t_INH
t_INL
PT CLOCK
t_IS
t_IH
INPUT
OUTPUT
AI03101
t_INO
Table 104. Input Macrocell Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
t_IS
Input Setup Time
(Note 1)
0
ns
t_IH
Input Hold Time
(Note 1)
15
+ 10 ns
t_INH
NIB Input High Time
(Note 1)
9
ns
t_INL
NIB Input Low Time
(Note 1)
9
ns
t_INO
NIB Input to Combinatorial Delay
(Note 1)
34
+ 2 + 10 ns
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t_AVLX and t_LXAX.
Table 105. Input Macrocell Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
t_IS
Input Setup Time
(Note 1)
0
ns
t_IH
Input Hold Time
(Note 1)
25
+ 20 ns
t_INH
NIB Input High Time
(Note 1)
12
ns
t_INL
NIB Input Low Time
(Note 1)
12
ns
t_INO
NIB Input to Combinatorial Delay
(Note 1)
46
+ 4 + 20 ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t_AVLX and t_LXAX.
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