UPSD3212C Datasheet, PDF (111/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Port D – Functionality and Structure
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). See Figure 57 and Figure 58.
This port does not support Address Out Mode, and
therefore no Control Register is required. Of the
eight bits in the Port D registers, only Bits 2 and 1
are used to configure pins PD2 and PD1.
Port D can be configured to perform one or more
of the following functions:
s MCU I/O Mode
s CPLD Output – External Chip Select (ECS1-
ECS2)
s CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
s Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
s CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
s PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Figure 57. Port D Structure
DATA OUT
REG.
DQ
WR
ECS[ 2:1]
READ MUX
P
D
B
DATA OUT
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
PORT D PIN
DIR REG.
DQ
WR
ENABLE PRODUCT
TERM (.OE)
CPLD - INPUT
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