UPSD3212C Datasheet, PDF (135/152 Pages) STMicroelectronics – Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

UPSD3212C, UPSD3212CV
Table 101. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate⁽¹⁾
Unit
Maximum Frequency
External Feedback
1/(t_S+t_CO)
22.2
MHz
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
28.5
MHz
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
40.0
MHz
t_S
Input Setup Time
20
+ 4 + 20
ns
t_H
Input Hold Time
0
ns
t_CH
Clock High Time
Clock Input
15
ns
t_CL
Clock Low Time
Clock Input
10
ns
t_CO
Clock to Output Delay
Clock Input
25
– 6 ns
t_ARD
CPLD Array Delay
Any
macrocell
25
+4
ns
t_MIN
Minimum Clock Period⁽²⁾
t_CH+t_CL
25
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) t_CLCL = t_CH + t_CL.
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