LSM9DS1 Datasheet, PDF (16/72 Pages) –

Module specifications
LSM9DS1
2.4.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Symbol
Table 7. I²C slave timing values
Parameter
I²C Standard mode⁽¹⁾
Min
Max
f_(SCL)
SCL clock frequency
0
t_w(SCLL)
SCL clock low time
4.7
t_w(SCLH)
SCL clock high time
4.0
t_su(SDA)
SDA setup time
250
t_h(SDA)
SDA data hold time
0
t_h(ST)
START condition hold time
4
t_su(SR)
Repeated START condition
setup time
4.7
100
3.45
t_su(SP)
STOP condition setup time
4
t_w(SP:SR)
Bus free time between STOP
and START condition
4.7
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 4. I²C slave timing diagram
I²C Fast mode ⁽¹⁾
Min
Max
0
400
1.3
0.6
100
0
0.9
0.6
0.6
0.6
1.3
Unit
kHz
µs
ns
µs
µs
67$57
6'$
5(3($7('
67$57
WVX65
WZ6365
67$57
6&/
WVX6'$
WK6'$
W_VX63
6723
WK67
WZ6&//
WZ6&/+
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
16/72
DocID025715 Rev 3