S70GL01GN00 Datasheet, PDF (81/83 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit™ Process Technology

Advance Information
Erase And Programming Performance
Parameter for Each S29GL512N
Sector Erase Time
Chip Erase Time
S29GL512N
Total Write Buffer Programming
Time (Note 3)
Total Accelerated Effective Write
Buffer Programming Time (Note 3)
Chip Program Time
S29GL512N
Typ
(Note 1)
0.5
256
Max
(Note 2)
3.5
1024
240
200
492
Unit
sec
sec
Comments
Excludes 00h programming prior
to erasure (Note 5)
µs
Excludes system level
µs
overhead (Note 6)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of 90°C, V_CC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10 on page 54 and Table 11 on page 57 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol Parameter Description
C_IN
C_OUT
C_IN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T_A = 25°C, f = 1.0 MHz.
Test Setup
V_IN = 0
V_OUT = 0
V_IN = 0
BGA
BGA
BGA
Typ Max
4.2
5.0
5.4
6.5
3.9
4.7
Unit
pF
pF
pF
June 1, 2005 S70GL01GN00_00_A1
S70GL01GN00 MirrorBit^TM Flash
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