S70GL01GN00 Datasheet, PDF (66/83 Pages) SPANSION – 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit™ Process Technology

Advance Information
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device
is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to Table 12 on page 65 to compare outputs for DQ2 and DQ6.
Figure 6, on page 63 shows the toggle bit algorithm in flowchart form, and the
section DQ2: Toggle Bit II explains the algorithm. See also the RY/BY#: Ready/
Busy# subsection. Figure 18, on page 76 shows the toggle bit timing diagram.
Figure 19, on page 76 shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 63 and Figure 19, on page 76 for the following discus-
sion. Whenever the system initially begins reading toggle bit status, it must read
DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the
first read. After the second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device success-
fully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 did not go high. The system may continue to monitor the tog-
gle bit and DQ5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure
6, on page 63).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a
specified internal pulse count limit. Under these conditions DQ5 produces a 1, in-
dicating that the program or erase cycle was not successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location
that was previously programmed to 0. Only an erase operation can change a
0 back to a 1. Under this condition, the device halts the operation, and when the
timing limit is exceeded, DQ5 produces a 1.
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure began. (The sector erase timer does not apply to
the chip erase command.) If additional sectors are selected for erasure, the entire
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S70GL01GN00 MirrorBit^TM Flash
S70GL01GN00_00_A1 June 1, 2005